Electronic devices must meet maximum electromagnetic interference (EMI) radiation limits as specified by the U.S. FCC and other comparable regulatory agencies in other countries. New FCC requirements call for PC motherboards to be able to pass EMI tests “open box,” so manufacturers will not be able to rely on the shielding provided by the case in meeting EMI requirements.
An EMI suppression-enabled clock IC can reduce the system radiated EMI. The reduction in radiated EMI can result in dramatic cost savings for the system. Conventional techniques for reducing EMI include ground planes, filtering components, shielding, and spread spectrum modulated system clocks.
In the spread spectrum technique, instead of concentrating all of a frequency reference's energy on a single frequency, the energy is spread out by modulating the frequency. The modulation results in the energy being spread over a frequency range, instead of being concentrated on one particular frequency. Since the FCC and other regulatory bodies are concerned with peak emissions, not average emissions, the reduction in peak energy due to spread spectrum modulation will help a product meet FCC requirements.
One type of spread spectrum modulation is center modulation (e.g., +/−). A center modulated clock provides the same system processing performance as for a CPU using a non-modulated clock. However, system designers are concerned about overboosting processors. If a processor designed for a 100 MHz reference is used with a reference that spends most of the time at 100.5 MHz, the processor will be operating at a higher than rated speed during that period of time. To alleviate this concern, modulation can be specified as “down only,” e.g., −0.5%. A −0.5% modulation, in the same 100 MHz example, would vary the frequency from 99.5 to 100 MHz. This is achieved by moving the center frequency down. What is specified as “100 MHz, with −0.5% modulation” can really be thought of as “99.75 MHz with +/−0.25% modulation.” Using “down only” modulation results in a performance degradation of a CPU, as the nominal 100 MHz signal is now less than 100 MHz.
If the spread spectrum clock generator could be configured for the spread spectrum modulation to be switched on and off, a system could have reduced EMI while still providing top performance when needed. However, during the transition period when the spread spectrum modulation is switching on or switching off, the frequency can undershoot or overshoot the rated input frequency range of the CPU. When the undershoot or overshoot exceeds the clock input frequency range of the processor, tracking loss and hanging can result.
Referring to FIG. 1, a block diagram of a circuit 10 illustrating a conventional phase lock loop based spread spectrum clock generator is shown. The circuit 10 generates a signal OUT in response to (i) a reference signal REF and a command signal SSON. The signal REF is presented to an input prescaler 12 and a multiplexer 14. The signal OUT is presented to a feedback prescaler 20 and a multiplexer 22. The signal SSON is presented to (i) the control inputs of the multiplexers 14 and 22 and (ii) the spread spectrum circuitry 26. In response to the command signal SSON, (i) the multiplexer 14 selects between the reference signal REF and an output of the input prescaler 12, (ii) the multiplexer 22 selects between the output signal OUT and an output of the feedback prescaler 20 and (iii) the spread spectrum circuitry modulates the signal out.
Referring to FIG. 2, a timing diagram and an oscilloscope tracing illustrating signals of the circuit 10 are shown. The timing diagram illustrates that a transition 30 in the signal SSON results in an immediate transition at the control inputs of the multiplexers 14 and 22. A portion 40 of the oscilloscope tracing illustrates the large transient response of the circuit 10 when spread spectrum modulation is switched on.